平头哥-芯片STA资深工程师/专家-上海

面议

上海市本科5-10年

岗位职责

Inafast-paced,leading-edgeenvironmentwithendlesspossibilitiesofinnovatingandlearning,youwillberesponsibleforleadinganddefiningtimingsignoffdesignmethodologiesofcomplexandworldclasschips/IPs.Inthisposition,yourresponsibilitiesmayinclude,butnotbelimitedto:

•Definingandimplementingsignoffmethodologyforallareasrelatedtotiminganalysis,CircuitQuality,Extractionandnoiseglitchanalysis；

•DevelopingrobustASICdesignandverificationmethodologytomeetperformancerequirementsincludingPVTcornerdefinitionfordesignconvergence,clockuncertaintyrequirements,timingbudgeting,repeaterplanning,automaticconstraints/exceptionsgeneration&management,andotherkeydifferentiatingcapabilitiesforquality&efficienttimingclosure；

•Workingcloselywithprocesstechnologyteamtounderstandprocesscharacteristicsandsettingappropriatedesignconstraintstomodelon-chipvariationeffects,power-supplyvariation,processagingandotherPV/Simiscorrelationeffectsintiminganalysisflows；

•EngagingcloselywithDesignteamstounderstandthedesign&convergencechallengesandderivemethodstoproviderecipeswithafocusonPPA&TAToptimizations；

•Developingtimingflows,understanddesignrequirements/objectivesanddevelopsignoffconditionsandmilestonechecklistsappropriatewiththedesignprojectgoals.Workwith3rdpartyEDAvendorstoresolveissuesanddriveimprovementsindesignconvergenceandsignoff；

•Leadfullchiptimingsignoffwork,includingSDCqualitycheck,timingawarephysicalimplementationguide,timinganalysisandsignoff.

任职要求

Theidealcandidateshouldexhibitbehavioraltraitsthatindicate:

•Self-motivatorwithstrongproblem-solvingskills

•Excellentinterpersonalskills,includingwrittenandverbalcommunication

•Abilitytoworkaspartofateamandcollaborateinahigh-pacedatmosphere

•Abilitytoprovidetechnicaldirectiontotheteamandinfluenceprojectexecutionandmethodology

Qualifications

•Mtech/BtechEngineeringDegreeinfieldofElectrical,Electronics,ComputerSciencewith2+/10+yrsofrelevantRTL2GDSexperience

•DemonstratedabilityinareasofTiminganalysis,timingconvergence,SI/Noiseanalysis,Signoffquality(PVT,processvariationeffects,guardbanding,etc),TimingECOs,Noisemodelling,.libs

•Expertiseandin-depthknowledgeofindustrystandardEDAtools(Timing,Synthesis,P&R)andASICdesignflowisrequired

•Multi-voltagescenariosdesignhandlingknowledgeisexpected.STAclosure/convergenceexecutionwithLowpowerdesignclosureisanaddedadvantage

•Proficiencyinscriptinglanguage,suchas,Tclrequired,perl/Pythonisaplus

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