Sr. ASIC Design Engineer (J11032)

1. Responsible for digital chip implementation from RTL to GDSII, which includes Lint/CDC check, logic synthesis, formal, SDC/UPF check and STA signoff.

2. Responsible for chip power solution including RTL/Gate level power estimation and power reduction, peak current analysis, silicon power correlation & debug.

3. Working closely with design & backend team for IP & Chip PPA improvement

4. Responsible for ASIC design methodology research and flow enhancement, interfacing with EDA vendors on technology.

任职资格:

Requirement

1. Bachelor/Master degree or above, major in Electrical Engineering, Computer Engineering or related with 5+ years working experience.

2. Hands on experience on logic Synthesis/ STA/ Low power, have good knowledge on IC process from RTL design to physical design

3. Familiar with EDA tools and design methodology, such as Spyglass/DC/PT/LEC/PTPX/Redhawk, familiar with sdc/upf.

4. Prefer but not limit to have experience on low power design/DFT/physical design

5. Hard-working, teamwork and self-motivated