资深数字IC设计验证工程师

1. RTL级和线网级仿真

2. 基于环境的随机约束验证

3. SVA系统级验证

4. 功能/断言覆盖率创建以及追踪覆盖率收敛

对于拥有以下经验技能者更佳：

1. 熟悉IEEE

802.3协议标准

2. 熟悉以太网交换机

3. 熟悉数字设计（例，时序收敛）

4. 熟悉System Verilog或者 UVM testbench

5. 精通脚本语言例如c shell,perl, Makefile

Develop and maintain Ethenet/Serdes/GBE verification of :

1. RTL and netlist simulation

2. Constrained-Random-Verification based environment

3. System level verification with SVA

4. Create Functional/Assertion Coverage and drive Coverage Closure

Experienced with below skillset is plus :

1. Familiar with IEEE

802.3 standard

2. Familiar with Ethernet Switch

3. Familiar with digital design (incl. timing closure)

4. Familiar with System Verilog or UVM testbench

5. Scripting languages such as C shell, Perl, Makefile