数字IC后端工程师
2.5-4万上海市本科不限经验
职位描述
Job Description:
As the ASIC Backend Engineer, you will be working closely with the front end ASIC team to synthesize the RTL, clean up the timing, go through the backend flows to deliver the tape-out.
Perform floorplan, physical synthesis, clock tree and clock gating design, power, routing, layout , integration and physical verification.
做为数字后端工程师,需要配合前端工程师从综合RTL代码开始，收敛时序，经历整个后端流程，直到成功流片。
主要从事标准单元以及各种IP位置摆放,时钟树的插入，时钟控制单元的设计，功耗分析，绕线，以及整个芯片的物理验证。
Required Experience:
Strong understanding of backend ASIC design flow, go through synthesis, DFT, floor planning, clock tree synthesis, place and route, SI analysis, timing closure, LVS, DRC.
Hands-on experience in low power design(UPF flow) and deep sub micron technology(22nm or below).
Familiar with the EDA tools of ICC2，Innovus, Primetime, Calibre, redhawk, etc.
Perl/TCL/Shell skills is a plus.
A self-starter that is motivated and a good team player is expected.
At least 3 years’ experience.
BSEE required, MSEE preferred.
相关要求：
1、理解及掌握后端流程，熟悉综合、DFT、布局规划、时钟树综合、SI分析、时序收敛、LVS（版图与代码比对）、DRC（设计规则违例）等各个环节。
2、有深亚微米工艺下（22nm以下）的低功耗设计经验尤佳。
3、熟悉EDA工具，如 ICC2，Innovus, Primetime, Calibre, redhawk等。
4、Perl/TCL/Shell 各种脚本语言技能尤佳。
5、3年工作经验以上。
6、相关专业本科学历要求， 硕士为佳。
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