平头哥-DDR验证工程师-深圳
深圳市本科应届
岗位职责
* Work with Architecture and Software teams to ensure DDR micro-architecture and design is fully verified/validated across multiple platforms
* Define testplan for specific block level design and execute the tesplan to achieve function verfication closure
* Development of reusable block level UVM verification enviroment with checker/monitor/driver etc,
任职要求
* Masters degree desired, Bachelor's degree in CS/EE is required. 3+ years of relevant experience in ASIC verification field.
* Should have the test plan definition and execution experience
* Fluent in System Verilog and scripting languages such as Python or Perl.
* Must have intimate knowledge of UVM methodology.
* Experience in the verification of DDR IP.
* Knowledgeable about assertions and functional coverage
* Experience with code coverage, formal verification tools; familiarity with evolving verification methodologies.
* Experience with ARM based C/Assemblly test is a big plus
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