DRAM Design/Verification(薪资面议)

1. Make the verification plan based on Spec and internal design request for completely cover function and timing verification.

2. Build the digital and mix-signal verification testbench to support the verification at the whole DRAM chip level.

3. Develop the behavior model for the fullchip and array based on the memory structure and functionality.

4. Verification methodology development to automate the procedure and improve the verification coverage.

5. Coordinate with design team to debug the design.

Requirement：

1. Knowledge and understanding of CMOS circuit design.

2. Familiar with EDA tools such as Spectre, finesim, NC-verilog, VCS etc.

3. Experience in SystemVerilog, UVM is a plus.

4. Experience in DRAM product verification is a plus.

5. Good team player and communication skills.

6. Good learning competency, self-motivated in a flexible and dynamic environment.